Designing Control Logic for a Single-Cycle Processor

The Missing Piece: Telling the Datapath What to Do

The datapath described earlier in this series contains multiplexers, an ALU, and memory units, but none of them know on their own what operation to perform for a given instruction. That decision is made by a separate piece of hardware called the Control Unit, which examines the instruction and generates the appropriate signals to drive every controllable element in the datapath.

Where Control Signals Come From

The control unit's decisions are based primarily on the instruction's Opcode field, and in some cases additional Funct fields, both of which were introduced earlier in this series when discussing instruction encoding. Since these fields sit in fixed bit positions across instruction formats, the control unit can extract them directly and use simple combinational logic to determine what the rest of the datapath should do.

Key Control Signals in a Single-Cycle Design

A handful of representative control signals illustrate how this works.

• ALUOp tells the ALU which specific operation to perform, such as addition for a load instruction's address calculation or subtraction for a branch comparison.
• MemRead and MemWrite enable reading from or writing to data memory, active only for load and store instructions respectively.
• RegWrite enables writing a result back into the register file, active for arithmetic and load instructions but not for stores or branches.
• Branch indicates whether the current instruction is a conditional branch, used together with the ALU's comparison result to decide whether to update the PC with a branch target address.
• MemtoReg selects, through a multiplexer, whether the value written into the register file comes from the ALU result or from data memory.

Tracing an Instruction Through the Control Logic

Consider how these signals differ across three instruction types executing on the same datapath.

For an "add" instruction:
ALUOp = addition, RegWrite = 1,
MemRead = 0, MemWrite = 0, Branch = 0

For a "load" instruction:
ALUOp = addition (address calculation),
MemRead = 1, RegWrite = 1, MemtoReg = 1

For a "branch" instruction:
ALUOp = subtraction (comparison),
Branch = 1, RegWrite = 0, MemWrite = 0

The same physical hardware handles all three instruction types correctly simply because the control unit changes which signals are active, routing data along a different effective path through the same shared datapath each time.

Why a Single-Cycle Design Is a Useful Starting Point

In this design, every instruction completes fully within one clock cycle, no matter how simple or complex it is. This makes the control logic conceptually simple to design and reason about, since there is no need to track partially completed instructions across multiple cycles. This simplicity, however, comes with a significant performance cost that becomes clear once pipelining is introduced later in this series, since the clock cycle length must be long enough to accommodate even the slowest instruction.