Why Arithmetic Needs Careful Hardware Design
At the software level, addition and subtraction appear as simple operators. At the hardware level, they must be implemented using physical circuits built from a limited number of logic gates, and those circuits must correctly handle a fixed number of bits, detect when a result cannot be represented, and do all of this fast enough to execute billions of times per second.
One Circuit for Both Addition and Subtraction
Rather than building two separate circuits, hardware reuses a single Adder circuit for both operations. This is possible because of how numbers are represented in Two's Complement, discussed earlier in this series: subtracting a number is equivalent to adding its negation.
a − b = a + (−b)Since negating a number in two's complement only requires inverting its bits and adding one, a subtraction instruction can reuse the same adder hardware as addition, with a small amount of extra circuitry to perform this negation on one operand first.
What Overflow Means and Why It Matters
Overflow occurs when the true mathematical result of an operation cannot fit within the fixed number of bits available to represent it. Because every register and memory word has a fixed width, a computation that should logically produce a larger value than that width allows will produce an incorrect, wrapped-around result unless overflow is detected.
Overflow Rules Differ for Signed and Unsigned Numbers
Whether a particular result counts as overflow depends on how the numbers are interpreted.
- For
Unsigned Numbers, overflow occurs when addition produces a result that requires more bits than are available — conceptually, a carry out of the most significant bit. - For
Signed Numbers, overflow occurs specifically when adding two positive numbers produces a negative result, or when adding two negative numbers produces a positive result — a sign that the true result was too large in magnitude to fit correctly.
Because these two rules are different, the same bit pattern and the same addition operation can be considered valid under one interpretation and an overflow under the other.
How RISC-V Handles Overflow
RISC-V takes a deliberate design approach here: ordinary arithmetic instructions such as add and sub do not automatically trap or raise an exception on signed overflow. Instead, overflow detection, when needed, is handled explicitly by software using additional comparison instructions, keeping the core arithmetic hardware simple and consistent with the earlier design principle of making the common case fast and letting software handle less frequent, more complex conditions.
Why This Distinction Matters in Practice
A programmer working with values close to the boundary of a data type's representable range, such as very large sums or counters that increment for a long time, must be aware that unsigned and signed interpretations of the identical stored bits can silently produce very different, and sometimes incorrect, results if overflow is not properly checked.