Turning a Single-Cycle Datapath into a Pipelined One

Why the Single-Cycle Datapath Cannot Simply Run Faster

Pipelining does not mean reusing the exact same single-cycle datapath and clocking it more quickly. Since five different instructions occupy five different stages simultaneously, the hardware for each stage must be physically separated, and the partial results of an instruction still in progress must be preserved as it moves from one stage to the next.

Pipeline Registers: Preserving State Between Stages

Between every pair of adjacent pipeline stages, a Pipeline Register stores all the values an instruction needs to carry forward into the next stage.

IF/ID register: holds the fetched instruction and incremented PC
ID/EX register: holds decoded register values, immediate, and control signals
EX/MEM register: holds ALU result, register value for stores, and control signals
MEM/WB register: holds the value to be written back and control signals

Each of these registers updates once per clock cycle, allowing one instruction's partial results to sit safely in a register while the next instruction's results are simultaneously being computed one stage earlier.

Control Signals Must Travel With the Instruction

In the single-cycle design covered earlier in this series, control signals were generated and used within the same cycle. In a pipelined design, a control signal generated during decode might not be needed until several cycles later, once the instruction reaches the memory or write-back stage. To handle this, control signals are carried forward through the same pipeline registers alongside the data they apply to, ensuring each signal arrives at the correct stage at the correct time for its own specific instruction.

An Example: Following a Load Instruction Through the Pipeline

Consider a load instruction moving through all five stages over five clock cycles.

Cycle 1 (IF): fetch the load instruction
Cycle 2 (ID): decode it, read base register, generate control signals
Cycle 3 (EX): ALU adds base register and offset to form the address
Cycle 4 (MEM): read the value from data memory at that address
Cycle 5 (WB): write the retrieved value into the destination register

At every one of these cycles, other instructions are simultaneously occupying the other four pipeline stages, each carrying their own data and control signals through their own pipeline registers without interfering with the load instruction's progress.

Why This Structural Change Matters

This separation of stages using pipeline registers is what makes overlapped execution physically possible. Without it, the hardware for a later stage would have no reliable way of knowing which instruction's data it is currently supposed to be working on, since multiple instructions occupy the datapath's different regions at the same instant.