Infrastructure, Systems, and Connectivity
Underneath every value a program manipulates and every instruction a processor executes lies a fixed-width string of bits. This article explains how signed and unsigned numbers are represented and interpreted differently from the same binary pattern, and how machine instructions themselves are encoded into rigid binary fields that hardware can decode at high speed.
Beyond arithmetic, processors need to manipulate individual bits and alter their execution path based on conditions. This article covers the core logical operations used for bit manipulation and explains how conditional branching and looping are built from a small set of comparison-based instructions.
Calling a function seems simple in high-level code, but at the hardware level it requires a careful protocol for saving return addresses, passing arguments, and preserving register values. This article explains how procedure calls are implemented using dedicated registers and a stack, then covers how processors represent human-readable text as sequences of encoded characters.
A 32-bit instruction cannot fit a large constant or a far-away memory address directly inside it, and multiple processors sharing memory cannot safely update the same data without coordination. This article explains how RISC-V builds large immediate values and addresses out of smaller pieces, and how atomic instructions allow parallel programs to synchronize safely.
Turning a C program into something the operating system can actually run involves several distinct translation stages, each producing a different intermediate file. This article walks through that full pipeline from compiler to loader, then applies the concepts from this chapter to a complete, realistic example: translating a C sorting routine into RISC-V assembly step by step.
In C, arrays and pointers often look interchangeable, and many programmers treat them as if they were the same thing. At the hardware level, however, they compile down to noticeably different instruction sequences with different performance characteristics. This article compares the two approaches using RISC-V assembly to show exactly why pointer-based code is often faster.
After covering operations, operands, encoding, and control flow, it is worth pausing to correct a handful of persistent misconceptions about instruction sets that even experienced programmers sometimes hold. This article closes out the instruction-set chapter by addressing these fallacies directly and summarizing why understanding machine instructions matters beyond academic curiosity.
Arithmetic looks trivial in software but requires careful circuit design and explicit overflow handling in hardware. This article explains how a processor's adder circuit performs both addition and subtraction using the same hardware, and how overflow conditions are detected and handled for signed and unsigned numbers.
Multiplication is far more hardware-intensive than addition, since it fundamentally involves repeated addition and shifting. This article walks through the conceptual algorithm hardware uses to multiply binary numbers, explains why the result needs twice the bit width of the inputs, and covers how signed multiplication differs from the unsigned case.
Division is the most hardware-intensive of the basic arithmetic operations, involving repeated subtraction and comparison rather than a single-pass circuit. This article explains the conceptual long-division algorithm hardware follows, how quotient and remainder are produced together, and the special edge cases like division by zero that hardware must explicitly handle.
Integers cannot represent fractional values or the enormous range of magnitudes scientific and financial computing requires. This article explains how floating-point numbers encode a sign, exponent, and fraction into a fixed number of bits following the IEEE 754 standard, and covers the precision tradeoffs and rounding issues that come with representing real numbers this way.
Modern processors often need to apply the same simple operation to many small data values simultaneously, such as adjusting brightness across millions of image pixels. This article explains subword parallelism, how a wide register can be split into several smaller lanes processed in a single instruction, and how real-world extensions like SIMD and AVX apply this idea in commercial hardware.
