Infrastructure, Systems, and Connectivity
Matrix multiplication is one of the most common and performance-critical operations in scientific computing and machine learning. This article shows how subword parallelism accelerates this operation in practice, then closes out the arithmetic chapter by addressing common misconceptions about computer arithmetic and summarizing the core lessons from addition through floating point.
Before a processor can be built, its designers must agree on a shared set of rules for how digital circuits behave over time. This article introduces what building a processor actually involves, the two broad categories of implementation covered in this chapter, and the foundational logic design conventions that make circuit behavior predictable.
A datapath is the physical circuitry that moves data through a processor as it executes an instruction. This article breaks down the essential hardware building blocks needed to fetch, decode, and execute instructions, and shows how they are wired together to form a functioning, if simplified, processor datapath.
A datapath alone does nothing without control signals telling it what to do for each instruction. This article explains how control logic reads an instruction's opcode and function fields to generate the exact signals needed to route data correctly, and walks through how a complete single-cycle implementation executes different instruction types.
A single-cycle processor wastes enormous amounts of hardware idle time since every instruction must fit within the length of the slowest possible instruction. This article introduces pipelining as a solution, explains the classic assembly-line analogy, breaks down the standard five-stage pipeline, and covers why pipelining increases instruction throughput without making any individual instruction faster.
Overlapping instruction execution requires more than just running the same single-cycle hardware faster; it requires physically separating each pipeline stage with storage elements and duplicating control logic across stages. This article explains how pipeline registers preserve instruction state between stages and how control signals travel alongside data through the pipeline.
Overlapping instruction execution creates a serious problem when one instruction needs a result that a previous instruction has not finished computing yet. This article explains what data hazards are, how forwarding solves most of them without losing any performance, and why some situations still require the pipeline to stall.
Branches create a unique problem for pipelining: the processor must fetch the next instruction before it even knows whether a branch will be taken. This article explains what control hazards are, how branch prediction and delayed resolution attempt to minimize their cost, and what happens when a prediction turns out to be wrong.
Not every instruction executes as expected — some trigger error conditions like an undefined opcode or an arithmetic overflow that the processor must respond to safely. This article explains what exceptions are, how a pipelined processor detects and handles them without corrupting program state, and why exceptions are treated similarly to control hazards.
A single pipeline can only advance one instruction into each stage per cycle, which caps its performance at roughly one instruction per clock. This article explains how processors go beyond that limit by issuing multiple instructions simultaneously, the hardware duplication this requires, and the fundamental limits imposed by dependencies between instructions.
Theoretical pipeline concepts take concrete shape in real commercial processors, which vary widely in pipeline depth and issue width depending on their design goals. This article compares how the ARM Cortex-A53 and Intel Core i7 implement pipelining differently for power efficiency versus raw performance, then shows how instruction-level parallelism accelerates matrix multiplication in practice.
After covering datapaths, pipelining, hazards, and real-world processor comparisons, it is time to correct a handful of persistent misconceptions about how processors actually behave. This article addresses common fallacies about pipelining and performance, then ties together the full journey from simple datapaths to superscalar execution covered throughout this chapter.
