A clear and structured exploration of how computer hardware and software interact at a fundamental level. It covers processor design, instruction execution, pipelining, memory hierarchy, parallelism, and the core principles that determine system performance. Using a modern and simplified instruction set architecture, it builds a strong foundation for understanding how computers and servers actually work under the hood.
Multiplication is far more hardware-intensive than addition, since it fundamentally involves repeated addition and shifting. This article walks through the conceptual algorithm hardware uses to multiply binary numbers, explains why the result needs twice the bit width of the inputs, and covers how signed multiplication differs from the unsigned case.
Division is the most hardware-intensive of the basic arithmetic operations, involving repeated subtraction and comparison rather than a single-pass circuit. This article explains the conceptual long-division algorithm hardware follows, how quotient and remainder are produced together, and the special edge cases like division by zero that hardware must explicitly handle.
Integers cannot represent fractional values or the enormous range of magnitudes scientific and financial computing requires. This article explains how floating-point numbers encode a sign, exponent, and fraction into a fixed number of bits following the IEEE 754 standard, and covers the precision tradeoffs and rounding issues that come with representing real numbers this way.
Modern processors often need to apply the same simple operation to many small data values simultaneously, such as adjusting brightness across millions of image pixels. This article explains subword parallelism, how a wide register can be split into several smaller lanes processed in a single instruction, and how real-world extensions like SIMD and AVX apply this idea in commercial hardware.
Matrix multiplication is one of the most common and performance-critical operations in scientific computing and machine learning. This article shows how subword parallelism accelerates this operation in practice, then closes out the arithmetic chapter by addressing common misconceptions about computer arithmetic and summarizing the core lessons from addition through floating point.
Before a processor can be built, its designers must agree on a shared set of rules for how digital circuits behave over time. This article introduces what building a processor actually involves, the two broad categories of implementation covered in this chapter, and the foundational logic design conventions that make circuit behavior predictable.
A datapath is the physical circuitry that moves data through a processor as it executes an instruction. This article breaks down the essential hardware building blocks needed to fetch, decode, and execute instructions, and shows how they are wired together to form a functioning, if simplified, processor datapath.
A datapath alone does nothing without control signals telling it what to do for each instruction. This article explains how control logic reads an instruction's opcode and function fields to generate the exact signals needed to route data correctly, and walks through how a complete single-cycle implementation executes different instruction types.
A single-cycle processor wastes enormous amounts of hardware idle time since every instruction must fit within the length of the slowest possible instruction. This article introduces pipelining as a solution, explains the classic assembly-line analogy, breaks down the standard five-stage pipeline, and covers why pipelining increases instruction throughput without making any individual instruction faster.
Overlapping instruction execution requires more than just running the same single-cycle hardware faster; it requires physically separating each pipeline stage with storage elements and duplicating control logic across stages. This article explains how pipeline registers preserve instruction state between stages and how control signals travel alongside data through the pipeline.
Overlapping instruction execution creates a serious problem when one instruction needs a result that a previous instruction has not finished computing yet. This article explains what data hazards are, how forwarding solves most of them without losing any performance, and why some situations still require the pipeline to stall.
Branches create a unique problem for pipelining: the processor must fetch the next instruction before it even knows whether a branch will be taken. This article explains what control hazards are, how branch prediction and delayed resolution attempt to minimize their cost, and what happens when a prediction turns out to be wrong.
