A clear and structured exploration of how computer hardware and software interact at a fundamental level. It covers processor design, instruction execution, pipelining, memory hierarchy, parallelism, and the core principles that determine system performance. Using a modern and simplified instruction set architecture, it builds a strong foundation for understanding how computers and servers actually work under the hood.
When multiple processor cores each have their own private cache but share the same underlying memory, a serious correctness problem emerges: different cores can end up with conflicting views of the same memory location. This article explains what cache coherence means, why it becomes necessary in multicore systems, and how snooping-based protocols keep every core's cached data consistent.
A single storage drive can fail at any time, potentially destroying valuable data with no warning. This article explains how RAID combines multiple disks to improve reliability, performance, or both, covering the tradeoffs between mirroring, striping, and parity-based approaches.
Theoretical cache and memory concepts take concrete form in real commercial processors with multiple cache levels and carefully tuned sizes. This article compares real memory hierarchies in ARM and Intel processors, shows how cache blocking accelerates matrix multiplication in practice, and closes out the memory hierarchy chapter by addressing common misconceptions.
Writing software that correctly and efficiently uses multiple processors is fundamentally harder than writing sequential code. This article explains why parallel programming introduces unique challenges around coordination and diminishing returns, then covers the classic Flynn's taxonomy that categorizes parallel hardware into SISD, MIMD, SIMD, and related models.
A single processor core often sits idle waiting for slow memory operations to complete, wasting valuable execution resources. This article explains how hardware multithreading lets a core rapidly switch between multiple independent instruction streams to fill those idle moments, covering both fine-grained and simultaneous multithreading approaches.
Multicore processors are the most common form of parallel hardware today, but the way their cores actually share memory varies in important ways. This article explains the shared memory multiprocessor model, contrasts uniform and non-uniform memory access designs, and covers how the operating system and programmer coordinate work across cores.
A GPU takes the SIMD idea covered earlier in this series to an extreme scale, running thousands of lightweight threads simultaneously to process massive amounts of independent data. This article explains why GPUs are architecturally so different from CPUs, how their thread execution model works, and what kinds of workloads benefit most from this design.
Beyond a single chip, parallelism extends to entire buildings full of independent computers working together. This article explains the shift from shared memory multiprocessing to clusters of separate machines, introduces the concept of warehouse-scale computing, and covers the network topologies that connect these independent machines efficiently.
A cluster of machines is only useful if it can communicate efficiently both internally and with the outside world. This article covers the networking layers involved in cluster communication, the tradeoffs between latency and bandwidth at scale, and how clusters connect to external networks and users.
Measuring the performance of a parallel system requires different tools and metrics than measuring a single-core processor. This article covers the specialized benchmarks used to evaluate multiprocessor systems, explains how to model scaling behavior as more processors are added, and revisits Amdahl's Law in the context of real-world performance measurement.
Comparing a CPU and a GPU fairly requires a model that accounts for both computational throughput and memory bandwidth limits together. This article introduces the roofline model used to compare real hardware like the Intel Core i7 and NVIDIA Tesla GPU, then shows how matrix multiplication is accelerated across multiple processors as the final practical application of this chapter's parallel concepts.
After covering everything from thread-level parallelism to warehouse-scale computing, it is worth correcting persistent misconceptions about parallel systems that even experienced engineers sometimes hold. This article addresses common fallacies about scaling and parallel hardware, then closes out the parallel processing chapter by tying together the full journey from a single instruction to a building full of cooperating machines.
