A clear and structured exploration of how computer hardware and software interact at a fundamental level. It covers processor design, instruction execution, pipelining, memory hierarchy, parallelism, and the core principles that determine system performance. Using a modern and simplified instruction set architecture, it builds a strong foundation for understanding how computers and servers actually work under the hood.
Not every instruction executes as expected — some trigger error conditions like an undefined opcode or an arithmetic overflow that the processor must respond to safely. This article explains what exceptions are, how a pipelined processor detects and handles them without corrupting program state, and why exceptions are treated similarly to control hazards.
A single pipeline can only advance one instruction into each stage per cycle, which caps its performance at roughly one instruction per clock. This article explains how processors go beyond that limit by issuing multiple instructions simultaneously, the hardware duplication this requires, and the fundamental limits imposed by dependencies between instructions.
Theoretical pipeline concepts take concrete shape in real commercial processors, which vary widely in pipeline depth and issue width depending on their design goals. This article compares how the ARM Cortex-A53 and Intel Core i7 implement pipelining differently for power efficiency versus raw performance, then shows how instruction-level parallelism accelerates matrix multiplication in practice.
After covering datapaths, pipelining, hazards, and real-world processor comparisons, it is time to correct a handful of persistent misconceptions about how processors actually behave. This article addresses common fallacies about pipelining and performance, then ties together the full journey from simple datapaths to superscalar execution covered throughout this chapter.
No single memory technology is simultaneously fast, large, and cheap. This article introduces the concept of a memory hierarchy that combines several different memory technologies to approximate the speed of the fastest one at the cost of the cheapest, then walks through the core technologies that make up each level.
A cache works because programs tend to access the same or nearby data repeatedly rather than randomly. This article explains the principle of locality that makes caching effective, how a direct-mapped cache locates data using an address, and what happens on a cache hit versus a cache miss.
Not all cache misses are the same, and understanding their causes is the first step toward improving performance. This article covers how to calculate the real performance impact of caching using miss rate and miss penalty, classifies the three common causes of cache misses, and explains practical strategies for reducing each type.
Memory hardware is not perfectly reliable; electrical noise and physical defects can silently flip stored bits. This article explains how error detection and correction codes let hardware notice, and in many cases automatically fix, these corrupted values before they cause incorrect program behavior.
A single physical computer can appear to run several completely separate operating systems at once, each unaware of the others' existence. This article explains what a virtual machine actually is, how a hypervisor manages this illusion, and why this technology matters for both server consolidation and system security.
Programs behave as if they have access to a huge, private block of memory, even though physical RAM is limited and shared among many running processes. This article explains how virtual memory creates this illusion through address translation, how page tables and the TLB make translation fast, and what happens when needed data is not currently in physical memory.
Caches and virtual memory appear at first glance to be very different systems, yet both are answering the exact same four fundamental questions. This article shows how those four questions unify block placement, block identification, block replacement, and write handling across every level of the memory hierarchy, from tiny caches to disk-backed virtual memory.
A cache does not just store data passively; hardware control logic must sequence through several distinct steps to handle a miss correctly. This article explains how a finite-state machine models this control logic, walks through the states involved in handling a cache hit and a cache miss, and shows why this formal model makes cache controller design easier to reason about.
