In this section, we explore the world of programming, algorithms, networks, and infrastructure
In C, arrays and pointers often look interchangeable, and many programmers treat them as if they were the same thing. At the hardware level, however, they compile down to noticeably different instruction sequences with different performance characteristics. This article compares the two approaches using RISC-V assembly to show exactly why pointer-based code is often faster.
After covering operations, operands, encoding, and control flow, it is worth pausing to correct a handful of persistent misconceptions about instruction sets that even experienced programmers sometimes hold. This article closes out the instruction-set chapter by addressing these fallacies directly and summarizing why understanding machine instructions matters beyond academic curiosity.
Arithmetic looks trivial in software but requires careful circuit design and explicit overflow handling in hardware. This article explains how a processor's adder circuit performs both addition and subtraction using the same hardware, and how overflow conditions are detected and handled for signed and unsigned numbers.
Multiplication is far more hardware-intensive than addition, since it fundamentally involves repeated addition and shifting. This article walks through the conceptual algorithm hardware uses to multiply binary numbers, explains why the result needs twice the bit width of the inputs, and covers how signed multiplication differs from the unsigned case.
Division is the most hardware-intensive of the basic arithmetic operations, involving repeated subtraction and comparison rather than a single-pass circuit. This article explains the conceptual long-division algorithm hardware follows, how quotient and remainder are produced together, and the special edge cases like division by zero that hardware must explicitly handle.
Integers cannot represent fractional values or the enormous range of magnitudes scientific and financial computing requires. This article explains how floating-point numbers encode a sign, exponent, and fraction into a fixed number of bits following the IEEE 754 standard, and covers the precision tradeoffs and rounding issues that come with representing real numbers this way.
Modern processors often need to apply the same simple operation to many small data values simultaneously, such as adjusting brightness across millions of image pixels. This article explains subword parallelism, how a wide register can be split into several smaller lanes processed in a single instruction, and how real-world extensions like SIMD and AVX apply this idea in commercial hardware.
Matrix multiplication is one of the most common and performance-critical operations in scientific computing and machine learning. This article shows how subword parallelism accelerates this operation in practice, then closes out the arithmetic chapter by addressing common misconceptions about computer arithmetic and summarizing the core lessons from addition through floating point.
Before a processor can be built, its designers must agree on a shared set of rules for how digital circuits behave over time. This article introduces what building a processor actually involves, the two broad categories of implementation covered in this chapter, and the foundational logic design conventions that make circuit behavior predictable.
A datapath is the physical circuitry that moves data through a processor as it executes an instruction. This article breaks down the essential hardware building blocks needed to fetch, decode, and execute instructions, and shows how they are wired together to form a functioning, if simplified, processor datapath.
A datapath alone does nothing without control signals telling it what to do for each instruction. This article explains how control logic reads an instruction's opcode and function fields to generate the exact signals needed to route data correctly, and walks through how a complete single-cycle implementation executes different instruction types.
A single-cycle processor wastes enormous amounts of hardware idle time since every instruction must fit within the length of the slowest possible instruction. This article introduces pipelining as a solution, explains the classic assembly-line analogy, breaks down the standard five-stage pipeline, and covers why pipelining increases instruction throughput without making any individual instruction faster.
