In this section, we explore the world of programming, algorithms, networks, and infrastructure
Programs behave as if they have access to a huge, private block of memory, even though physical RAM is limited and shared among many running processes. This article explains how virtual memory creates this illusion through address translation, how page tables and the TLB make translation fast, and what happens when needed data is not currently in physical memory.
Caches and virtual memory appear at first glance to be very different systems, yet both are answering the exact same four fundamental questions. This article shows how those four questions unify block placement, block identification, block replacement, and write handling across every level of the memory hierarchy, from tiny caches to disk-backed virtual memory.
A cache does not just store data passively; hardware control logic must sequence through several distinct steps to handle a miss correctly. This article explains how a finite-state machine models this control logic, walks through the states involved in handling a cache hit and a cache miss, and shows why this formal model makes cache controller design easier to reason about.
When multiple processor cores each have their own private cache but share the same underlying memory, a serious correctness problem emerges: different cores can end up with conflicting views of the same memory location. This article explains what cache coherence means, why it becomes necessary in multicore systems, and how snooping-based protocols keep every core's cached data consistent.
A single storage drive can fail at any time, potentially destroying valuable data with no warning. This article explains how RAID combines multiple disks to improve reliability, performance, or both, covering the tradeoffs between mirroring, striping, and parity-based approaches.
Theoretical cache and memory concepts take concrete form in real commercial processors with multiple cache levels and carefully tuned sizes. This article compares real memory hierarchies in ARM and Intel processors, shows how cache blocking accelerates matrix multiplication in practice, and closes out the memory hierarchy chapter by addressing common misconceptions.
Writing software that correctly and efficiently uses multiple processors is fundamentally harder than writing sequential code. This article explains why parallel programming introduces unique challenges around coordination and diminishing returns, then covers the classic Flynn's taxonomy that categorizes parallel hardware into SISD, MIMD, SIMD, and related models.
A single processor core often sits idle waiting for slow memory operations to complete, wasting valuable execution resources. This article explains how hardware multithreading lets a core rapidly switch between multiple independent instruction streams to fill those idle moments, covering both fine-grained and simultaneous multithreading approaches.
Multicore processors are the most common form of parallel hardware today, but the way their cores actually share memory varies in important ways. This article explains the shared memory multiprocessor model, contrasts uniform and non-uniform memory access designs, and covers how the operating system and programmer coordinate work across cores.
A GPU takes the SIMD idea covered earlier in this series to an extreme scale, running thousands of lightweight threads simultaneously to process massive amounts of independent data. This article explains why GPUs are architecturally so different from CPUs, how their thread execution model works, and what kinds of workloads benefit most from this design.
Beyond a single chip, parallelism extends to entire buildings full of independent computers working together. This article explains the shift from shared memory multiprocessing to clusters of separate machines, introduces the concept of warehouse-scale computing, and covers the network topologies that connect these independent machines efficiently.
A cluster of machines is only useful if it can communicate efficiently both internally and with the outside world. This article covers the networking layers involved in cluster communication, the tradeoffs between latency and bandwidth at scale, and how clusters connect to external networks and users.
